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C8051T610/1/2/3/4/5/6/7
Mixed-Signal Byte-Programmable EPROM MCU
Analog Peripherals
High-Speed 8051 μC Core
-
10-Bit ADC (‘T610/1/2/3/6 only)
-
Pipelined instruction architecture; executes 70% of
?
?
?
?
Up to 500 ksps
Up to 21, 17, or 13 external inputs
VREF from external pin, Internal Regulator or V DD
Internal or external start of conversion source
-
-
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
-
? Built-in temperature sensor
Comparators
? Programmable hysteresis and response time
? Configurable as interrupt sources
Digital Peripherals
- 29/25/21 Port I/O with high sink current capability
- Hardware enhanced UART, SMBus?, and
?
Configurable as reset source (Comparator 0)
enhanced SPI? serial ports
? Low current (<0.5 μA)
On-Chip Debug
- C8051F310 can be used as code development ?
platform; Complete development kit available
- On-chip debug circuitry facilitates full speed, ?
non-intrusive in-system debug
- Provides breakpoints, single stepping, ?
inspect/modify memory and registers
Supply Voltage 1.8 to 3.6 V
- On-chip LDO for internal core supply
- Built-in voltage supply monitor
Memory
- 1280 Bytes internal data RAM (256 + 1024)
- 16 or 8 kB byte-programmable EPROM code mem-
ory
Temperature Range: –40 to +85 °C
ANALOG
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with five
capture/compare modules and PWM functionality
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports crystal-less UART operation
- External oscillator: RC, C, or CMOS Clock
- Can switch between clock sources on-the-fly; useful
in power saving modes
Packages
- 32-pin LQFP (C8051T610/2/4)
- 28-pin QFN (C8051T611/3/5)
- 24-pin QFN (C8051T616/7)
DIGITAL I/O
PERIPHERALS
UART
Port 0
A
M
U
X
10-bit
500 ksps
ADC
+
-
+
SMBus
SPI
PCA
Timer 0
Port 1
Port 2
TEMP
SENSOR
-
VOLTAGE
Timer 1
Timer 2
Port 3
C8051T610/1/2/3/6 only COMPARATORS
Timer 3
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
16 kB/8 kB
EPROM
8051 CPU
(25MIPS)
1280 B
SRAM
14
INTERRUPTS
DEBUG
CIRCUITRY
POR
WDT
Rev 1.1 6/11
Copyright ? 2011 by Silicon Laboratories
C8051T610/1/2/3/4/5/6/7
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